1. Field of the Invention
The present invention relates to an A/D conversion circuit for converting an analog signal into a digital signal in a time domain.
This application claims a priority based on Japanese Patent Application No. 2010-057907 filed on Mar. 15, 2010, the entire contents of which is incorporated hereby by reference.
2. Description of Related Art
There is conventional technique of converting an analog signal to a digital signal in a time domain using inverting circuits including logical elements in which a delay time of a pulse signal is changed with a size of an analog signal (analog input signal) applied as a supply voltage. For example, a pulse phase difference encoding circuit including a ring oscillator, in which the power of 2 inverting circuits are connected and a pulse signal circles the inverting circuits, is disclosed in Japanese Patent No. 3455982. In the pulse phase difference encoding circuit, a transit position and a circling number of the pulse signal are detected from the ring oscillator, and a digital signal is generated from the transit position and the circling number of the pulse signal according to a size of an analog signal.
FIG. 12 shows a configuration of the pulse phase difference encoding circuit disclosed in Japanese Patent No. 3455982. The pulse phase difference encoding circuit 200 shown in FIG. 12 includes a ring oscillator 40, a pulse selector and encoder 41, a counter and latch 42, and a multiplexer 43.
The ring oscillator 40 has a configuration in which a power of 2-stage (32-stage) inverting circuits NAND1, INV2 to INV31, and NAND32 are connected in series. The inverting circuits are connected in the order of NAND1, INV2 to INV31, and NAND32. An external driving signal PA is input to one input terminal of NAND 1, and an output signal from NAND32 is input to the other input terminal of NAND1. An output signal from INV18 is input to one input terminal of NAND32, and an output signal from INV31 is input to the other input terminal of NAND32. Accordingly, a pulse signal based on the driving signal PA input to the ring oscillator 40 circles the inverting circuits in the ring oscillator 40. Further, an external analog input signal VA is applied for the highest potential for all the inverting circuits in the ring oscillator 40, and GND is applied for the lowest potential for all the inverting circuits.
The pulse selector and encoder 41 detects a transit position of the pulse signal transiting the ring oscillator 40, in synchronization with an external control signal PB, based on output signals D1 to D32 from the inverting circuits in the ring oscillator 40, encodes the transit position, and outputs the encoded transit position to the multiplexer 43 of a subsequent stage. An output signal D33 indicating the encoded transit position, which is output from the pulse selector and encoder 41, is for example a 4-bit digital signal.
Based on the output signal D32 from the NAND 32, the counter and latch 42 detects a circling number of the pulse signal transiting the ring oscillator 40 (the number of pulse signals detected from the output signal D32) in synchronization with the external control signal PB, and outputs the circling number to the multiplexer 43 of the subsequent stage. An output signal D34 indicating the circling number, which is output from the counter and latch 42, is for example a 6-bit digital signal.
The multiplexer 43 synthesizes the transit position D33 of the pulse signal detected by the pulse selector and encoder 41 with the circling number D34 of the pulse signal detected by the counter and latch 42, in which the transit position D33 forms lower bits and the circling number D34 forms upper bits, to thereby generate a digital signal according to a size of the analog input signal VA in synchronization with the external control signal PB, and outputs the digital signal to a circuit of a subsequent stage, which is not shown. A digital signal DA output from the multiplexer 43 is, for example, a 10-bit signal.
A correspondence relationship in configuration between a pulse phase difference encoding circuit 4 shown in FIG. 3 of Japanese Patent No. 3455982 and the pulse phase difference encoding circuit 200 shown in FIG. 12 is as follows:
Even-stage ring oscillator 2=ring oscillator 40
Pulse selector 6 and encoder 8=pulse selector and encoder 41
Counter 10 and latch 12=counter and latch 42
Multiplexer 18=multiplexer 43
In order for the pulse signal to stably circle the ring oscillator 40 including the power of 2-stage (32-stage) inverting circuits, it is necessary to cause two pulse signals (a main pulse and a reset pulse) to transit the ring oscillator 40, as shown in FIGS. 13 and 14. FIGS. 13 and 14 show logical states of the respective inverting circuits in the ring oscillator 40. Numbers 1, 2 to 31, and 32 shown in a top of FIGS. 13 and 14 correspond to NAND1, INV2 to INV31, and NAND32.
The main pulse is a pulse signal that iteratively transits all the inverting circuits from NAND1 to NAND32 in a period of time in which the external driving signal PA is at an “H” level. Further, the reset pulse is a pulse signal that transits all the inverting circuits from NAND32 to INV3 only in one period in the period of time in which the external driving signal PA is at the “H” level. The reset pulse is a pulse for resetting a logical state of each inverting circuit, which is inverted by the transit of the main pulse, to an initial state. “The reset pulse transiting only in one period” means that the reset pulse is extinct every period and is newly generated by the main pulse.
Specifically, at a time 0, each inverting circuit outputs a signal in a logical state shown in FIG. 13. At a time 1, the output of NAND 1 is inverted from an “H” level to an “L” level by the driving signal PA, and the main pulse starts transit of a first period. At a time 19, the reset pulse is generated when an output of NAND 32 is inverted from an “H” level to an “L” level by the main pulse at an “H” level output by INV18 at a time 18, and the reset pulse begins to transit.
At a time 33, the output of NAND1 is inverted from the “H” level to the “L” level by a main pulse at an “H” level output by NAND32 at a time 32, and the main pulse starts transit of a second period. At a time 51, the output of NAND 32 is inverted from the “H” level to the “L” level by a main pulse at an “H” level output by INV18 and a reset pulse at an “H” level output by INV31 at a time 50, to thereby generate a new reset pulse, and the reset pulse begins to transit. Even in subsequent times, the main pulse and the reset pulse transit the ring oscillator 40, as described above.
As described above, the main pulse iteratively transits all the inverting circuits from NAND1 to NAND32 as the output of NAND 32 is inverted from the “L” level to the “H” level by the transit of the main pulse. On the other hand, the reset pulse transits all the inverting circuits from NAND32 to INV31 only in one period as the output of INV18 is inverted from the “L” level to the “H” level by the transit of the main pulse.
When an odd number of inverting circuits are connected in series and an output signal from the inverting circuit of the last stage is input to the inverting circuit of the first stage, an oscillation operation can be performed through circling of one pulse signal. However, when an even numbers of inverting circuits are connected in series and an output signal from the inverting circuit of the last stage is input to the inverting circuit of the first stage, the logical state of each inverting circuit is fixed when one pulse signal is circled, and the oscillation operation cannot be performed.
Here, when the even number of inverting circuits are connected in series and the output signal from the inverting circuit of the last stage is input to the inverting circuit of the first stage, the oscillation operation can be performed through the transit of the two pulse signals (the main pulse and the reset pulse), as described above.
In order for the ring oscillator 40 to perform the oscillation operation through the transit of the two pulse signals, it is necessary to settle a logical state of INV31 earlier than a logical state of INV18, in an inverting operation according to the transit start of the reset pulse. For example, when both outputs of INV18 and INV31 are inverted from the “L” level to the “H” level at a time 50 of FIG. 14, an output of NAND 32 is inverted from the “H” level to the “L” level at a time 51 and the reset pulse starts the transit. However, when the relationship that the output of INV31 reaches the “H” level earlier than that of INV18 is not satisfied, the reset pulse is extinct and the ring oscillator 40 cannot perform the oscillation operation.
Thereby, as shown in FIGS. 17 and 18, in the inverting circuit of the even stage, a time period from an input signal being changed from the “H” level to a middle potential and an output signal being changed from the “L” level to the middle potential (hereinafter, TpdLH) is set to be longer than a time period from an input signal being changed from the “L” level to a middle potential to the output signal being changed from the “H” level to the middle potential (hereinafter, TpdHL). FIG. 17 corresponds to INV2, INV4, . . . , INV30, and FIG. 18 corresponds to NAND32. Further, as shown in FIGS. 15 and 16, in the inverting circuit of the odd stage, TpdLH is set to be shorter than TpdHL. FIG. 15 corresponds to INV3, INV5, . . . , INV31, and FIG. 16 corresponds to NAND 1.
According to the settings shown in FIGS. 15 to 18, when the input signal of the inverting circuit is changed from the “H” level to the “L” level, the output signal of the inverting circuit is changed from the “L” level to the “H” level, but a delay time (TpdLH) in the inverting circuit of the odd stage at this time is set to be shorter than that in the inverting circuit of the even stage. When the input signal of the inverting circuit is changed from the “L” level to the “H” level, the output signal of the inverting circuit is changed from the “H” level to the “L” level, but a delay time (TpdHL) in the inverting circuit of the even stage at this time may be set to be shorter than that in the inverting circuit of the odd stage. Thereby, when an output of the inverting circuit of a previous stage is inverted from the “L” level to the “H” level, the output of INV31 reaches the “H” level earlier than that of INV18.
When TpdHL>TpdLH, a time period of the “H” level is longer than that of the “L” level, and when TpdLH>TpdHL, the time period of the “H” level is shorter than that of the “L” level. FIG. 19A shows time periods of “H” and “L” levels in the inverting circuit of the odd stage, and FIG. 19B shows time periods of “H” and “L” levels in the inverting circuit of the even stage. In the examples of FIGS. 19A and 19B, when the time periods of the “H” and “L” levels are TH1 and TL1 in the inverting circuit of the even stage and the time periods of the “H” and “L” levels are TH2 and TL2 in the inverting circuit of the odd stage, TH1≠TL1 and TH2≠TL2, and TH1≠TH2 and TL1≠TL2, respectively.
The pulse selector and encoder 41 detects a logical state of each inverting circuit, i.e., the transit position of the pulse signal at the same time intervals in synchronization with the external control signal PB based on the output signals D1 to D32 from the respective inverting circuits. However, when the transit position of the pulse signal is not detected from an output of a circuit as a minimum unit, which is one set of the inverting circuit of the even stage and the inverting circuit of the odd stage, due to a difference between TpdLH and TpdHL in each inverting circuit as described above, the transit position of the pulse signal cannot be detected at the same time intervals.